Plated Through Hole Current Rating: Complete Guide for PCB Designers

May/21/2026

Everything you need to know about PCB Via Current Capacity, thermal limits, and design optimization

Plated Through Hole Current Rating: Complete Guide for PCB Designers

What You Will Learn

How plated through hole vias actually carry current
Current rating formulas based on thermal and electrical limits
Practical current capacity tables for common via sizes
Why single vias fail and how to prevent it
Techniques for handling high current with via arrays
Design guidelines that work in production

Understanding Plated Through Hole Technology

A plated through hole (PTH) via is more than just a hole in your PCB. It is a cylindrical copper barrel connecting layers, and when current flows through a via, it travels through this copper barrel. The resistance of that barrel determines both voltage drop and heat generation.

The critical misconception many engineers have: vias are just connections. Wrong. Vias are resistors, and at high currents, they are thermal liabilities. Understanding plated through hole current rating is essential for any Power Electronics Design.

The Anatomy of a Plated Through Hole

1、Barrel - The copper-plated cylindrical wall. This is your current path. Plating thickness typically 0.7-1.0 mil (18-25 micrometers) per side.

2、Pad - The circular copper landing on each surface. Provides mechanical strength and soldering surface.

3、Annular Ring - The copper ring surrounding the drilled hole. Must be minimum 5mil for manufacturability.

4、Plating Thickness - The copper inside the barrel. Usually 1oz (35 micrometers) finished, but varies by fab spec.

The Physics of Via Current Rating

Where the Current Actually Flows

Current in a via barrel flows along the cylindrical copper wall. The effective cross-sectional area is the circumference times the plating thickness:

A = pi x (D + t) x t

Where: D = drill diameter, t = plating thickness

For a 0.5mm drill with 25 micrometers plating:

Circumference: pi x 0.5mm = 1.57mm
Cross-sectional area: 1.57mm x 0.025mm = 0.039 mm2
Compare to a 100mil (2.54mm) wide trace at 35 micrometers thick: 0.089 mm2

Key insight: A single 0.5mm via has less than half the cross-sectional area of a modest power trace. This is why vias limit current capacity.

Thermal Limit vs. Electrical Limit

Vias have two distinct current limits:

Limit Type	What It Means	Typical Threshold
Electrical Limit	Voltage drop becomes unacceptable	Usually 10-50mV per via
Thermal Limit	Temperature rise damages the board	Usually 10-20 degrees C rise

In practice, thermal limits govern for most designs. A via that works electrically may still fail thermally by melting solder or delaminating the board.

Practical Current Rating Tables

Single Via Current Capacity (10 degrees C Rise)

0.3mm drill (12mil)

0.4mm drill (16mil)

0.5mm drill (20mil)

12A

0.7mm drill (28mil)

15A

0.8mm drill (32mil)

20A

1.0mm drill (40mil)

Note: These values assume 1oz (25 micrometers) finished copper plating, 20 degrees C ambient, still air, and no thermal relief. Your actual results may vary based on PCB construction and thermal environment.

Current Rating by Plating Thickness

Plating Weight	Finished Thickness	0.5mm Via Capacity	0.8mm Via Capacity
0.5 oz (HALT)	~12 micrometers	4A	8A
1 oz (standard)	~25 micrometers	8A	15A
2 oz	~50 micrometers	14A	26A
3 oz	~75 micrometers	20A	38A

Watch Out for Nominal Plating

IPC standards allow plating thickness to vary. Minimum spec might be 0.7 mil (18 micrometers) while the average is higher. Always design for minimum plating thickness unless your manufacturer guarantees otherwise.

The Via Resistance Problem

Calculating Via Resistance

R = rho x L / A

Where: rho = copper resistivity (1.7x10^-8 ohm-m), L = board thickness, A = barrel cross-section

Via Resistance Examples

Via Size	Board Thickness	Resistance	Voltage Drop at 10A
0.5mm drill	1.6mm	~1.1 mOhm	11 mV
0.8mm drill	1.6mm	~0.5 mOhm	5 mV
1.0mm drill	1.6mm	~0.25 mOhm	2.5 mV

Real-World Impact

For a 48V power bus with 10 vias carrying 20A:

Voltage drop: 10 x 1mOhm = 10mV per via chain
Power dissipation: I2R = 400 x 0.001 = 0.4W per via
With 10 vias in parallel: 0.04W total dissipation
But if one via opens? Now 0.4W in one via - thermal disaster

Why Single Vias Fail at High Current

Countless designs fail because engineers underestimated via current demands. Here is what happens:

The Failure Cascade

Current concentrated in single via
Via heats to 100C+
Solder joint weakens
Via opens or increases resistance
Current shifts to remaining vias
Thermal runaway begins

The Right Approach

Calculate total current requirement
Divide across multiple parallel vias
Include 50% redundancy margin
Verify thermal simulation
Prototype and measure temperature

High Current Via Design Techniques

Technique 1: Via Array (Most Common)

Spread current across multiple smaller vias:

Via Array Design Rules

Spacing: Minimum 0.5mm between via centers (prevents breakout)
Stagger: Offset rows like honeycomb for better copper distribution
Thermal Vias: Connect inner planes with dedicated thermal via clusters
Current sharing: All vias should be identical size for equal current distribution

Technique 2: Filled Vias

Fill vias with conductive epoxy or solid copper:

Filling Type	Current Capacity Gain	Cost Impact	Best For
Standard (empty)	1x baseline	Baseline	Low current
Conductive epoxy fill	1.5-2x improvement	+30-50%	Medium current
Copper overplate fill	2-3x improvement	+80-100%	High current
Solid copper (metal coin)	5-10x improvement	+200%+	Extreme current

Technique 3: Tented and Covered Vias

For production reliability, tenting or covering vias prevents solder wicking:

Tented: Solder mask covers the via, prevents solder entry
Plugged: Via filled with non-conductive material
Covered: Additional copper over the top

But be careful - tented vias can trap air during thermal cycling, causing reliability issues in high-temperature applications.

Technique 4: Via-in-Pad

Place vias directly in component pads:

Benefit: Minimizes inductance and resistance
Drawback: Risk of solder wicking into via
Solution: Fill or plug the via before assembly

Design Guidelines for Common Applications

Power Supply Rails

48V to 20A Power Rail Example

Step 1: Determine via requirements
Single 0.5mm via at 10A = 8A capacity (from table)
Need: 20A / 8A = 2.5 vias minimum

Step 2: Add safety margin (50%)
2.5 x 1.5 = 3.75, round up to 4 vias minimum

Step 3: Choose via arrangement
4 x 0.5mm vias in 2x2 array, 1mm spacing

Step 4: Verify trace width to via transition
Each via needs 100mil pad minimum = 4 x 100mil = 400mil trace width capacity

MOSFET Thermal Pad Connections

Power MOSFETs with thermal pads often require dozens of Thermal Vias:

Thermal pad size: Typically 4mm x 4mm for DPAK, larger for D2PAK
Vias required: 6x6 to 8x8 grid of 0.3-0.5mm vias
Fill method: Conductive epoxy preferred
Mask: No solder mask under thermal pad (direct metal contact)

IGBT and Power Module Connections

High-power modules need specialized approaches:

Press-fit terminals: Up to 100A per pin
Heatsink vias: Large thermal vias connected to copper spreaders
Busbar integration: Solder or bolt copper bars to PCB terminals

Thermal Considerations

How Vias Heat Up

A via heats up due to I2R losses in the copper barrel. The heat must escape through:

Conduction through pads to adjacent copper on the surface
Conduction through barrel to inner layer planes
Convection from the barrel surface to surrounding air
Radiation (minor contributor at typical PCB temperatures)

Thermal Via Placement Matters

A via surrounded by copper planes will run cooler than one in bare FR-4. Always connect high-current vias to inner copper planes with thermal via arrays.

Temperature Rise Estimation

For quick estimation without simulation:

delta-T = (I2 x R) / (h x A)

Where: h = convective heat transfer coefficient (~100 W/m2-K), A = surface area

This is an approximation. For critical designs, use thermal simulation or physical testing.

Manufacturing Considerations

IPC Standards for Vias

Parameter	IPC-A-600 Class 2	IPC-A-600 Class 3
Minimum annular ring	2 mil (0.05mm)	5 mil (0.13mm)
Voiding in barrel	less than 10%	less than 5%
Minimum drill size	0.25mm (10mil)	0.3mm (12mil)

Cost vs. Capability Trade-offs

Small vias (0.2-0.3mm): Cheap, limited current, harder to plate consistently
Medium vias (0.4-0.6mm): Best balance of cost and current
Large vias (0.8-1.0mm): Higher current, more expensive, plating uniformity issues
Blind/buried vias: Expensive, use only when necessary for routing

Testing Your Vias

Before production, verify Via Current Capacity with:

Resistance measurement: Each via should measure less than 2mOhm
Thermal imaging: IR camera under full load current
Thermal cycling: -40C to +125C, 500 cycles minimum
Cross-section analysis: Cut a sample via to verify plating thickness

Quick Reference: Via Current Capacity Summary

Current Range	Recommended Approach	Example Configuration
0-3A	Single standard via	1 x 0.4mm via
3-8A	Single larger via	1 x 0.8mm via, or 2 x 0.5mm
8-15A	Via array	3-4 x 0.5mm vias in array
15-30A	Via array + thermal planes	6-8 x 0.5mm + inner plane connection
30-50A	Filled vias + heavy copper	8-12 x 0.8mm filled + 2oz copper
50A+	Copper coins or busbars	Specialized construction required

Design Checklist

Calculate total current per net

Determine single via current capacity from tables

Size via array with 50% redundancy margin

Verify via-to-trace width transition

Connect vias to inner thermal planes

Specify plating thickness on fabrication drawing

Add thermal simulation for critical paths

Prototype and measure via temperatures

Document failure modes and margins

Common Mistakes to Avoid

Mistake 1: Assuming Via Data Sheet Ratings Apply

Manufacturer current ratings assume ideal conditions. Real boards have thermal gradients, non-uniform plating, and manufacturing variations. Always add margin.

Mistake 2: Ignoring Via-to-Pad Transitions

A 1mm via in a 0.5mm pad creates a stress concentration. Pad diameter should be minimum 2x drill diameter.

Mistake 3: Forgetting About Thermal Cycling

CTE mismatch between copper and FR-4 causes via barrel cracks over time. This is accelerated at high temperatures and high currents.

Mistake 4: Using Blind Vias for Power

Blind vias are harder to plate uniformly and more expensive. Use through-hole vias for power distribution unless space absolutely requires otherwise.

Ready to Design Your High-Current Vias?

Start with conservative estimates, prototype with thermal imaging, and always verify before committing to production. The cost of a via redesign is trivial compared to field failures.

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